package and_expressions
  port type BitsPort(int b0, int b1, int b2, int b3)

  connector type Synchronize(BitsPort p, BitsPort q)
    define p q

    on p q provided (p.b0==q.b0 && p.b1==q.b1 && p.b2==q.b2 && p.b3==q.b3)
  end

  connector type Single(BitsPort p)
    define p
  end

  atom type Bits()
    data int b0
    data int b1
    data int b2
    data int b3

    export port BitsPort sync(b0, b1, b2, b3)

    place LOOP, END

    initial to LOOP
      do { b0=1; b1=0; b2=0; b3=0; }

    on sync from LOOP to LOOP
      do {
        if (b0==0) then
          b0=1;
        else if (b1==0) then
          b0=0;
          b1=1;
        else if (b2==0) then
          b0=0;
          b1=0;
          b2=1;
        else if (b3==0) then
          b0=0;
          b1=0;
          b2=0;
          b3=1;
        else
          b0=0;
          b1=0;
          b2=0;
          b3=0;
        fi fi fi fi
      }

    internal from LOOP to END
      provided (b0==0 && b1==0 && b2==0 && b3==0)
  end

  compound type AndExpressions()
    component Bits B1(), B2()

    connector Single single1(B1.sync)
    connector Single single2(B2.sync)
    connector Synchronize sync(B1.sync, B2.sync)
   
    priority single_sync1 single1:* < sync:*
    priority single_sync2 single2:* < sync:*
  end
end